--====================================================================
--                  USB TEST ver 0.1 for XILINX Edition
--           (C)Copyright 2003 Nahitafu all rights reserved.
--
--License: GPL(GNU General Public License).
--Contact: http://www.nahitech.com/
--=====================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity usbtest is
    Port (      CLK0      : in std_logic;
                CLK1      : in std_logic;
                CLK2      : in std_logic;
                CLK3      : in std_logic;
                USER      : inout std_logic_vector(36 downto 0);
                SD_D      : inout std_logic_vector(15 downto 0);
                SD_A      : out std_logic_vector(12 downto 0);
                SD_BS1    : out std_logic;
                SD_BS0    : out std_logic;
                SD_LDQM   : out std_logic;
                SD_UDQM   : out std_logic;
                SD_WEN    : out std_logic;
                SD_RAS    : out std_logic;
                SD_CAS    : out std_logic;
                SD_CLK    : out std_logic;
                SD_CKE    : out std_logic;
                SD_CS     : out std_logic;
                USB_D     : inout std_logic_vector(7 downto 0);
                USB_WR    : out std_logic;
                USB_RD    : out std_logic;
                USB_TXE   : in std_logic;
                USB_RXF   : in std_logic;
                USB_PWREN : in std_logic;
                USB_RSTO  : in std_logic
        );
end usbtest;

architecture Behavioral of usbtest is
    signal CLK          : std_logic;

    component USBIF port (
        CLK                : in std_logic;
        FT245_D            : inout std_logic_vector(7 downto 0);
        FT245_WR           : out std_logic;
        FT245_RD           : out std_logic;
        FT245_TXE          : in std_logic;
        FT245_RXF          : in std_logic;
        FT245_PWREN        : in std_logic;
        FT245_RSTO         : in std_logic;
        USB_Tx_DATA        : in std_logic_vector(7 downto 0);
        USB_Rx_DATA        : out std_logic_vector(7 downto 0);
        USB_RX_Ready       : in std_logic;
        USB_TX_Ready       : in std_logic;
        USB_Received       : out std_logic;
        USB_Transmitted    : out std_logic
    ); 
    end component;

    component CLKDLL port(
        CLKFB  : in std_logic;
        CLKIN  : in std_logic;
        RST    : in std_logic;
        CLK0   : out std_logic;
        CLK180 : out std_logic;
        CLK270 : out std_logic;
        CLK2X  : out std_logic;
        CLK90  : out std_logic;
        CLKDV  : out std_logic;
        LOCKED : out std_logic
    );
    end component;
    component BUFG port(
        I  : in std_logic;
        O  : out std_logic
    );
    end component;
    component IBUFG port(
        I  : in std_logic;
        O  : out std_logic
    );
    end component;

    signal CLK_I,CLK_O,CLK_2X : std_logic;
    signal CLK_1X_OP,CLK_2X_OP : std_logic;
    signal USB_TX_DATA      : std_logic_vector(7 downto 0);
    signal USB_RX_DATA      : std_logic_vector(7 downto 0);
    signal USB_TX_Ready     : std_logic;
    signal USB_Received     : std_logic;
    signal USB_Transmitted  : std_logic;

begin
    USER(36 downto 0)  <= (others=>'Z');
    CLK <= CLK0;

    usbif0 : USBIF port map (
        CLK                => CLK,
        FT245_D            => USB_D,
        FT245_WR           => USB_WR,
        FT245_RD           => USB_RD,
        FT245_TXE          => USB_TXE,
        FT245_RXF          => USB_RXF,
        FT245_PWREN        => USB_PWREN,
        FT245_RSTO         => USB_RSTO,
        USB_Tx_DATA        => USB_TX_DATA,
        USB_Rx_DATA        => USB_RX_DATA,
        USB_RX_Ready       => '1', -- always reveive ready
        USB_TX_Ready       => USB_TX_Ready,
        USB_Received       => USB_Received,
        USB_Transmitted    => USB_Transmitted
    );
    process(CLK) begin
        if(CLK'event and CLK='1') then
            if(USB_Received = '1') then
                USB_TX_Ready <= '1';
            elsif(USB_Transmitted = '1') then
                USB_TX_Ready <= '0';
            end if;
        end if;
        if((USB_RX_DATA >= x"61") and (USB_RX_DATA <= x"7A")) then
            USB_TX_DATA  <= USB_RX_DATA - x"20";
        else
            USB_TX_DATA  <= USB_RX_DATA;
        end if;
    end process;
end Behavioral;