----------------------------------------------
-- NP1003 SDRAM & USB template source file
-- (C) Copyright 2003 Nahitafu Nahitech
-- http://www.nahitech.com
----------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity main is
    Port (      CLK0      : in std_logic;
                CLK1      : in std_logic;
                CLK2      : in std_logic;
                CLK3      : in std_logic;
                USER      : inout std_logic_vector(36 downto 0);
                SD_D      : inout std_logic_vector(15 downto 0);
                SD_A      : out std_logic_vector(12 downto 0);
                SD_BS1    : out std_logic;
                SD_BS0    : out std_logic;
                SD_LDQM   : out std_logic;
                SD_UDQM   : out std_logic;
                SD_WEN    : out std_logic;
                SD_RAS    : out std_logic;
                SD_CAS    : out std_logic;
                SD_CLK    : out std_logic;
                SD_CKE    : out std_logic;
                SD_CS     : out std_logic;
                USB_D     : inout std_logic_vector(7 downto 0);
                USB_WR    : out std_logic;
                USB_RD    : out std_logic;
                USB_TXE   : in std_logic;
                USB_RXF   : in std_logic;
                USB_PWREN : in std_logic;
                USB_RSTO  : in std_logic
        );
end main;

architecture Behavioral of main is
    signal CLK          : std_logic;
    signal logicH       : std_logic;
    signal logicL       : std_logic;

    signal USB_STATE        : integer range 0 to 15;
    signal USB_RXF_node     : std_logic;
    signal USB_TXE_node     : std_logic;
    signal USB_RX_Ready     : std_logic;
    signal USB_TX_Ready     : std_logic;
    signal USB_Received     : std_logic;
    signal USB_Transmitted  : std_logic;
    signal USB_Tx_DATA      : std_logic_vector(7 downto 0);
    signal USB_Rx_DATA      : std_logic_vector(7 downto 0);
    signal USB_WR_node      : std_logic;
    signal USB_RD_node      : std_logic;

begin
    CLK <= CLK0;
    logicH <= '1';
    logicL <= '0';
--  SDRAM default pin condition
    SD_CLK    <= not CLK;
    SD_CS     <= '1';
    SD_RAS    <= '1';
    SD_CAS    <= '1';
    SD_CKE    <= '0';
    SD_WEN    <= '1';
    SD_D      <= (others=>'Z');
    SD_A      <= (others=>'0');
    SD_BS1    <= '0';
    SD_BS0    <= '0';
    SD_LDQM   <= '0';
    SD_UDQM   <= '0';

--  USB default pin condition
    USB_RD_node <= logicH;
    USB_WR_node <= logicL;
    USB_RD      <= USB_RD_node;
    USB_WR      <= USB_WR_node;
    USB_D       <= (others=>'Z');

--  USER I/O default pin condition
    USER(35 downto 0)  <= (others=>'0');
    -- USER(36) is used to avoid implementation error. see below

--  CLK processes
    process(CLK) begin
      if(CLK'event and CLK='1') then
        USER(36)           <= usb_txe and usb_rxf;
      end if;
    end process;

end Behavioral;