--==================================================================== -- USB Interface ver 0.1 for XILINX and FT245BM -- (C)Copyright 2003 Nahitafu all rights reserved. -- --License: GPL(GNU General Public License). --Contact: http://www.nahitech.com/ --===================================================================== library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity USBIF is Port ( CLK : in std_logic; FT245_D : inout std_logic_vector(7 downto 0); FT245_WR : out std_logic; FT245_RD : out std_logic; FT245_TXE : in std_logic; FT245_RXF : in std_logic; FT245_PWREN : in std_logic; FT245_RSTO : in std_logic; USB_Tx_DATA : in std_logic_vector(7 downto 0); USB_Rx_DATA : out std_logic_vector(7 downto 0); USB_RX_Ready : in std_logic; USB_TX_Ready : in std_logic; USB_Received : out std_logic; USB_Transmitted : out std_logic ); end USBIF; architecture Behavioral of USBIF is signal USB_STATE : integer range 0 to 15; signal FT245_RXF_node : std_logic; signal FT245_TXE_node : std_logic; signal FT245_WR_node : std_logic; signal FT245_RD_node : std_logic; begin FT245_RD <= FT245_RD_node; FT245_WR <= FT245_WR_node; process(CLK) begin if (CLK'event and CLK = '1') then FT245_RXF_node <= FT245_RXF; FT245_TXE_node <= FT245_TXE; end if; end process; process(CLK) begin if (CLK'event and CLK = '1') then case USB_STATE is when 0 => FT245_D <= (others=>'Z'); USB_Received <= '0'; USB_Transmitted <= '0'; if((FT245_RXF_node = '0') and (USB_RX_Ready = '1')) then FT245_RD_node <= '0'; -- effect at state 1 USB_STATE <= 1; elsif((FT245_TXE_node = '0') and (USB_TX_Ready = '1')) then USB_STATE <= 8; else FT245_RD_node <= '1'; FT245_WR_node <= '0'; end if; -- USB read sequence when 1 => USB_STATE <= 2; when 2 => USB_STATE <= 3; when 3 => USB_Rx_Data <= FT245_D; -- effect at state 4 USB_Received <= '1'; USB_STATE <= 4; when 4 => FT245_RD_node <= '1'; -- effect at state 5 USB_Received <= '0'; USB_STATE <= 5; when 5 => USB_STATE <= 6; when 6 => USB_STATE <= 7; when 7 => FT245_RD_node <= '1'; USB_STATE <= 0; -- USB write sequence when 8 => FT245_WR_node <= '1'; -- effect at state 9 FT245_D <= USB_Tx_DATA;-- effect at state 9 USB_STATE <= 9; when 9 => USB_STATE <= 10; when 10 => USB_STATE <= 11; when 11 => USB_STATE <= 12; when 12 => FT245_WR_node <= '0'; -- effect at state 13 USB_Transmitted <= '1'; USB_STATE <= 13; when 13 => FT245_D <= (others=>'Z');-- effect at state 14 USB_Transmitted <= '0'; USB_STATE <= 14; when 14 => USB_STATE <= 15; when 15 => USB_STATE <= 0; when others => USB_STATE <= 0; end case; end if; end process; end Behavioral;