--==================================================================== -- HASIC ver 0.1 for XILINX Edition -- (C)Copyright 2004 Nahitafu all rights reserved. -- --License: GPL(GNU General Public License). --Contact: http://www.nahitech.com/ --===================================================================== library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity hasic is generic( constant MAX_ROM_ADDR : integer := 5119; -- 10 of BLOCK RAMS constant CLK_FREQ_kHZ : integer := 28636; -- 28.63636MHz constant FUKAN_TIME_MS : integer := 50; -- 50ms constant SamplingRate_kHz : integer := 8; -- 8kHz constant MAX_HEs : integer := 4 -- num of overlapped "HE-"s ); Port ( CLK0 : in std_logic; CLK1 : in std_logic; CLK2 : in std_logic; CLK3 : in std_logic; USER : inout std_logic_vector(36 downto 0); SD_D : inout std_logic_vector(15 downto 0); SD_A : out std_logic_vector(12 downto 0); SD_BS1 : out std_logic; SD_BS0 : out std_logic; SD_LDQM : out std_logic; SD_UDQM : out std_logic; SD_WEN : out std_logic; SD_RAS : out std_logic; SD_CAS : out std_logic; SD_CLK : out std_logic; SD_CKE : out std_logic; SD_CS : out std_logic; USB_D : inout std_logic_vector(7 downto 0); USB_WR : out std_logic; USB_RD : out std_logic; USB_TXE : in std_logic; USB_RXF : in std_logic; USB_PWREN : in std_logic; USB_RSTO : in std_logic ); end hasic; architecture Behavioral of hasic is signal CLK : std_logic; component OBUF_F_24 is port (I : in std_logic;O : out std_logic); end component; -- wave form ROM image component RAMB4_S8 port ( DI : in STD_LOGIC_VECTOR (7 downto 0); EN : in STD_ULOGIC; WE : in STD_ULOGIC; RST : in STD_ULOGIC; CLK : in STD_ULOGIC; ADDR : in STD_LOGIC_VECTOR (8 downto 0); DO : out STD_LOGIC_VECTOR (7 downto 0) ); end component; signal BRAM_ADDR : std_logic_vector(12 downto 0); signal BRAM_DO0 : std_logic_vector(7 downto 0); signal BRAM_DO1 : std_logic_vector(7 downto 0); signal BRAM_DO2 : std_logic_vector(7 downto 0); signal BRAM_DO3 : std_logic_vector(7 downto 0); signal BRAM_DO4 : std_logic_vector(7 downto 0); signal BRAM_DO5 : std_logic_vector(7 downto 0); signal BRAM_DO6 : std_logic_vector(7 downto 0); signal BRAM_DO7 : std_logic_vector(7 downto 0); signal BRAM_DO8 : std_logic_vector(7 downto 0); signal BRAM_DO9 : std_logic_vector(7 downto 0); signal BRAM_DO : std_logic_vector(7 downto 0); -- usb interface component USBIF port ( CLK : in std_logic; FT245_D : inout std_logic_vector(7 downto 0); FT245_WR : out std_logic; FT245_RD : out std_logic; FT245_TXE : in std_logic; FT245_RXF : in std_logic; FT245_PWREN : in std_logic; FT245_RSTO : in std_logic; USB_Tx_DATA : in std_logic_vector(7 downto 0); USB_Rx_DATA : out std_logic_vector(7 downto 0); USB_RX_Ready : in std_logic; USB_TX_Ready : in std_logic; USB_Received : out std_logic; USB_Transmitted : out std_logic ); end component; signal USB_TX_DATA : std_logic_vector(7 downto 0); signal USB_RX_DATA : std_logic_vector(7 downto 0); signal USB_RX_Ready : std_logic; signal USB_TX_Ready : std_logic; signal USB_Received : std_logic; signal USB_Transmitted : std_logic; -- sampling rate generator signal SamplingCountMax : integer := CLK_FREQ_kHZ / SamplingRate_kHz; signal SamplingCount : integer range 0 to CLK_FREQ_kHZ / SamplingRate_kHz + 1; signal SamplingTiming : std_logic; -- DA converter signal DAC_OUT : std_logic; signal DAC_IN : std_logic_vector(9 downto 0); -- PUSH SWITCH signal SW_INPUT : std_logic; signal SW_TIMER_OUT : std_logic; signal SW_TIMER_OUTD : std_logic; signal SW_INPUT_PLS : std_logic; constant SW_COUNT_MAX : integer := CLK_FREQ_kHZ * FUKAN_TIME_MS; signal SW_COUNT : integer range 0 to SW_COUNT_MAX + 1; -- Wave form generator component dac is port ( CLK : in std_logic; DAC_IN : in std_logic_vector(9 downto 0); DAC_OUT : out std_logic ); end component; subtype ADDRCOUNT is integer range 0 to MAX_ROM_ADDR + 1; type COUNTER_ARRAY_T is ARRAY(0 to (MAX_HEs-1)) of ADDRCOUNT; signal COUNTER_ARRAY : COUNTER_ARRAY_T; signal SELECT_COUNT : std_logic_vector(1 downto 0); signal SELECT_COUNT_D : std_logic_vector((MAX_HEs-1) downto 0); signal COUNT_RESET : std_logic_vector((MAX_HEs-1) downto 0); signal PLAYCOUNT : std_logic_vector((MAX_HEs-1) downto 0); signal ADD_OUT : std_logic_vector(9 downto 0); begin USER(36) <= 'Z'; -- NC USER(35) <= 'Z'; -- NC USER(34) <= 'Z'; -- NC USER(33) <= '0'; -- output Low -- USER(32) <= 'Z'; -- SW input SW_INPUT <= USER(32); USER(31) <= 'Z'; -- NC USER(30) <= '1'; -- output High USER(29 downto 16) <= (others=>'Z'); obuf24_15 : OBUF_F_24 port map (I => DAC_OUT, O => USER(15)); obuf24_14 : OBUF_F_24 port map (I => DAC_OUT, O => USER(14)); USER(13 downto 1) <= BRAM_ADDR; obuf24_0 : OBUF_F_24 port map (I => DAC_OUT, O => USER(0)); CLK <= CLK0; SD_D <= (others=>'Z'); SD_A <= (others=>'0'); SD_BS1 <= '1'; SD_BS0 <= '1'; SD_LDQM <= '1'; SD_UDQM <= '1'; SD_WEN <= '1'; SD_RAS <= '1'; SD_CAS <= '1'; SD_CLK <= '0'; SD_CKE <= '1'; SD_CS <= '1'; process(CLK) begin if(CLK'event and CLK = '1') then if(SW_COUNT /= 0) then SW_COUNT <= SW_COUNT - 1; else if((SW_INPUT = '0') or (USB_Received = '1')) then -- PUSHED SW_TIMER_OUT <= '1'; SW_COUNT <= SW_COUNT_MAX; else -- NOT PUSHED SW_TIMER_OUT <= '0'; end if; end if; SW_TIMER_OUTD <= SW_TIMER_OUT; if((SW_TIMER_OUT = '1') and (SW_TIMER_OUTD = '0')) then SW_INPUT_PLS <= '1'; else SW_INPUT_PLS <= '0'; end if; end if; end process; process(CLK) begin if(CLK'event and CLK = '1') then if(SW_INPUT_PLS = '1') then SELECT_COUNT <= SELECT_COUNT + 1; end if; end if; end process; BRAM_ADDR <= conv_std_logic_vector(COUNTER_ARRAY(0),13) when(PLAYCOUNT(3 downto 2) = "00") else conv_std_logic_vector(COUNTER_ARRAY(1),13) when(PLAYCOUNT(3 downto 2) = "01") else conv_std_logic_vector(COUNTER_ARRAY(2),13) when(PLAYCOUNT(3 downto 2) = "10") else conv_std_logic_vector(COUNTER_ARRAY(3),13) when(PLAYCOUNT(3 downto 2) = "11") else (others => '0'); process(CLK) begin if(CLK'event and CLK = '1') then PLAYCOUNT <= PLAYCOUNT + 1; if(PLAYCOUNT = "0000") then ADD_OUT <= (others => '0'); elsif(PLAYCOUNT(1 downto 0) = "11") then ADD_OUT <= ADD_OUT + ("00" & BRAM_DO); end if; if(PLAYCOUNT = "0000") then DAC_IN <= ADD_OUT; end if; end if; end process; multi_HE_generator : for I in 0 to (MAX_HEs-1) generate process(CLK) begin if(CLK'event and CLK = '1') then if(conv_integer(SELECT_COUNT) = I) then SELECT_COUNT_D(I) <= '1'; else SELECT_COUNT_D(I) <= '0'; end if; if((conv_integer(SELECT_COUNT) = I) and (SELECT_COUNT_D(I) = '0')) then COUNT_RESET(I) <= '1'; else COUNT_RESET(I) <= '0'; end if; if(COUNT_RESET(I) = '1') then COUNTER_ARRAY(I) <= 0; elsif(COUNTER_ARRAY(I) /= MAX_ROM_ADDR) then if(SamplingTiming = '1') then COUNTER_ARRAY(I) <= COUNTER_ARRAY(I) + 1; end if; end if; end if; end process; end generate; SampleTimingGen : process(CLK) begin if(CLK'event and CLK = '1') then if(SamplingCount = SamplingCountMax) then SamplingCount <= 0; SamplingTiming <= '1'; else SamplingCount <= SamplingCount + 1; SamplingTiming <= '0'; end if; end if; end process; delta_sigma_dac : dac port map( CLK => CLK, DAC_IN => DAC_IN, DAC_OUT => DAC_OUT ); USB_RX_Ready <= '1'; USB_TX_Ready <= '0'; usbif0 : USBIF port map ( CLK => CLK, FT245_D => USB_D, FT245_WR => USB_WR, FT245_RD => USB_RD, FT245_TXE => USB_TXE, FT245_RXF => USB_RXF, FT245_PWREN => USB_PWREN, FT245_RSTO => USB_RSTO, USB_Tx_DATA => USB_TX_DATA, USB_Rx_DATA => USB_RX_DATA, USB_RX_Ready => USB_RX_Ready, USB_TX_Ready => USB_TX_Ready, USB_Received => USB_Received, USB_Transmitted => USB_Transmitted ); process(CLK) begin if(CLK'event and CLK = '1') then case (BRAM_ADDR(12 downto 9)) is when "0000" => BRAM_DO <= BRAM_DO0; when "0001" => BRAM_DO <= BRAM_DO1; when "0010" => BRAM_DO <= BRAM_DO2; when "0011" => BRAM_DO <= BRAM_DO3; when "0100" => BRAM_DO <= BRAM_DO4; when "0101" => BRAM_DO <= BRAM_DO5; when "0110" => BRAM_DO <= BRAM_DO6; when "0111" => BRAM_DO <= BRAM_DO7; when "1000" => BRAM_DO <= BRAM_DO8; when "1001" => BRAM_DO <= BRAM_DO9; when others => BRAM_DO <= (others => '0'); end case; end if; end process; ROM0 : RAMB4_S8 port map ( ADDR => BRAM_ADDR(8 downto 0), CLK => CLK, DI => (others=>'0'), EN => '1', RST => '0', WE => '0', DO => BRAM_DO0 ); ROM1 : RAMB4_S8 port map ( ADDR => BRAM_ADDR(8 downto 0), CLK => CLK, DI => (others=>'0'), EN => '1', RST => '0', WE => '0', DO => BRAM_DO1 ); ROM2 : RAMB4_S8 port map ( ADDR => BRAM_ADDR(8 downto 0), CLK => CLK, DI => (others=>'0'), EN => '1', RST => '0', WE => '0', DO => BRAM_DO2 ); ROM3 : RAMB4_S8 port map ( ADDR => BRAM_ADDR(8 downto 0), CLK => CLK, DI => (others=>'0'), EN => '1', RST => '0', WE => '0', DO => BRAM_DO3 ); ROM4 : RAMB4_S8 port map ( ADDR => BRAM_ADDR(8 downto 0), CLK => CLK, DI => (others=>'0'), EN => '1', RST => '0', WE => '0', DO => BRAM_DO4 ); ROM5 : RAMB4_S8 port map ( ADDR => BRAM_ADDR(8 downto 0), CLK => CLK, DI => (others=>'0'), EN => '1', RST => '0', WE => '0', DO => BRAM_DO5 ); ROM6 : RAMB4_S8 port map ( ADDR => BRAM_ADDR(8 downto 0), CLK => CLK, DI => (others=>'0'), EN => '1', RST => '0', WE => '0', DO => BRAM_DO6 ); ROM7 : RAMB4_S8 port map ( ADDR => BRAM_ADDR(8 downto 0), CLK => CLK, DI => (others=>'0'), EN => '1', RST => '0', WE => '0', DO => BRAM_DO7 ); ROM8 : RAMB4_S8 port map ( ADDR => BRAM_ADDR(8 downto 0), CLK => CLK, DI => (others=>'0'), EN => '1', RST => '0', WE => '0', DO => BRAM_DO8 ); ROM9 : RAMB4_S8 port map ( ADDR => BRAM_ADDR(8 downto 0), CLK => CLK, DI => (others=>'0'), EN => '1', RST => '0', WE => '0', DO => BRAM_DO9 ); end Behavioral;