library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity dac is
	generic (
		DAC_WIDTH : integer := 10
	);
    Port ( CLK     : in  std_logic;
           DAC_IN  : in  std_logic_vector((DAC_WIDTH - 1) downto 0);
           DAC_OUT : out std_logic
	);
end dac;

architecture Behavioral of dac is
	signal DeltaOut    : std_logic_vector((DAC_WIDTH + 1) downto 0);
	signal SigmaOut    : std_logic_vector((DAC_WIDTH + 1) downto 0);
begin

	DeltaOut <= SigmaOut(DAC_WIDTH + 1) & SigmaOut(DAC_WIDTH + 1) & DAC_IN;
	process(CLK) begin
		if(CLK'event and CLK = '1') then
			SigmaOut <= DeltaOut + SigmaOut;
			DAC_OUT <= SigmaOut(DAC_WIDTH);
		end if;
	end process;

end Behavioral;