MODULE csync13

TITLE 'SYNC GENERATOR Clock 13MHz'

//
//                     CSYNC13 Version 1.0
//
// Nahitafu's Free-IP
// Sync generator for standard color NTSC signal Version 1.0
// Clock frequency 13.500000MHz version
// (C)Copyright 2000 Nahitafu 
//
// see more detail --- http://member.nifty.ne.jp/nahitafu/
//
// This can be fitted to XILINX XC9536PC44C , XC9536XLPC44C
//

CLK		pin;	//Main clock 13.5MHz or 27MHz or 54MHz
ENA		pin;	//Clock enable input
RES		pin;	//Reset signal input

HSYNC		pin istype 'neg,reg';	//Horizontal sync
VSYNC		pin istype 'neg,reg';	//Vertical sync
CSYNC		pin istype 'neg,reg';	//Composit sync
FLD		pin istype 'pos,reg';	//Field ID
HD		pin istype 'pos,reg';	//Horizontal drive pulse
VD		pin istype 'pos,reg';	//Vertical drive pulse
HBLK		node istype 'pos,com';	//Horizontal blanking pulse
VBLK		node istype 'pos,reg';	//Vertical blanking pulse
BLK		pin istype 'neg,com';	//Blanking pulse
HSDOWN		node istype 'pos,com';	//Horizontal sync down signal
HSUP		node istype 'pos,com';	//Horizontal sync up signal
VSDOWN		node istype 'pos,com';	//Vertical sync down signal
VSUP		node istype 'pos,com';	//Vertical sync up signal
CSDOWN		node istype 'pos,com';	//Composit sync down signal
CSUP		node istype 'pos,com';	//Composit sync up signal
H20		node istype 'pos,com';	//Horizontal position is 20
H52		node istype 'pos,com';	//Horizontal position is 52
H84		node istype 'pos,com';	//Horizontal position is 84
H385		node istype 'pos,com';	//Horizontal position is 385
H449		node istype 'pos,com';	//Horizontal position is 449
H481		node istype 'pos,com';	//Horizontal position is 481
H814		node istype 'pos,com';	//Horizontal position is 814
EQDUR		node istype 'pos,reg';	//EQ pulse duration
VSDUR		node istype 'pos,reg';	//Vertical seration pulse duration

[HPOS9..HPOS0]	pin istype 'pos,reg';	//Horizontal position
[VPOS9..VPOS0]	pin istype 'pos,reg';	//Vertical position

HPOS = [HPOS9..HPOS0];
VPOS = [VPOS9..VPOS0];

equations
	HSYNC.CLK = CLK;
	VSYNC.CLK = CLK;
	CSYNC.CLK = CLK;
	FLD.CLK = CLK;
	HPOS.CLK = CLK;
	VPOS.CLK = CLK;
	EQDUR.CLK = CLK;
	VSDUR.CLK = CLK;
	HD.CLK = CLK;
	VD.CLK = CLK;
	VBLK.CLK = CLK;

//condition of special horizontal position
	when(HPOS == 20) then  H20  = 1;else H20 = 0;
	when(HPOS == 52) then  H52  = 1;else H52 = 0;
	when(HPOS == 84) then  H84  = 1;else H84 = 0;
	when(HPOS == 385) then H385 = 1;else H385 = 0;
	when(HPOS == 449) then H449 = 1;else H449 = 0;
	when(HPOS == 481) then H481 = 1;else H481 = 0;
	when(HPOS == 814) then H814 = 1;else H814 = 0;

//HV counter increment
when(RES) then{
	HPOS := 0;
	VPOS := 1;
	HSYNC := 'H';				
	VSYNC := 'H';				
	CSYNC := 'H';				
	HD := 0;
	VD := 0;
	VBLK := 1;
	FLD := 'H';				
	EQDUR := 'H';				
	VSDUR := 'L';				
}
else{
	when(ENA) then{
		when (HPOS == 857) then{
			HPOS := 0;
//****for debuging
//			when(VPOS == 30) then{
//				VPOS := 260;
//			}
//			else when(VPOS == 292) then{
//				VPOS := 522;
//			}
			when(VPOS == 525) then{
				VPOS := 1;
			}
			else{
				VPOS := VPOS + 1;
			}
		}
		else{		
			HPOS := HPOS.FB + 1;
			VPOS := VPOS.FB;
		}
	}
	else{
		HPOS := HPOS.FB;
		VPOS := VPOS.FB;
	}
 
//condition of HSYNC updown
	when(H20) then HSDOWN = 1;
	else HSDOWN = 0;
	when(H84) then HSUP = 1;
	else HSUP = 0;
//condition of VSYNC updown
 	when(((VPOS == 4) & H20) # ((VPOS == 266) & H449)) then VSDOWN = 1;
	else VSDOWN = 0;
 	when(((VPOS == 7) & H20) # ((VPOS == 269) & H449)) then VSUP = 1;
	else VSUP = 0;
//HSYNC trandition
	when(HSUP) then HSYNC := 1;
	else when(HSDOWN) then HSYNC := 0;
	else HSYNC := HSYNC.FB;
//VSYNC trandition
	when(VSUP) then VSYNC := 1;
	else when(VSDOWN) then VSYNC := 0;
	else VSYNC := VSYNC.FB;
//FLD trandition
	when((VPOS == 266) & H449) then FLD := 0;
	else when((VPOS == 4) & H20) then FLD := 1;
	else FLD := FLD.FB;
//VD signal (equal to inverting EQDUR signal)
	when(((HPOS==0)&(VPOS==1))#((HPOS==429)&(VPOS==263))) then VD := 0;
	else when(((HPOS==0)&(VPOS==10))#((HPOS==429)&(VPOS==272))) then VD := 1;
	else VD := VD.FB;
//HD signal
	when(HPOS==0) then HD := 0;
	else when(HPOS==84) then HD := 1;
	else HD := HD.FB;
//HBLK signal (Horizontal blanking duration , positive logic)
	when((HPOS>=0) & (HPOS<=146)) then HBLK = 1;
	else HBLK = 0;
//VBLK signal (Vertical blanking duration , positive logic)
	when(((HPOS==0)&(VPOS==0))#((HPOS==429)&(VPOS==263))) then VBLK := 1;
	else when(((HPOS==0)&(VPOS==20))#((HPOS==429)&(VPOS==282))) then VBLK := 0;
	else VBLK := VBLK.FB;
//BLK signal (Blanking duration , negative logic)
	when(HBLK # VBLK) then BLK = 0;
	else BLK = 1;	
//trandition of VS duration signal
	when(((HPOS==0)&(VPOS==4))#((HPOS==429)&(VPOS==266))) then VSDUR := 1;
	else when(((HPOS==0)&(VPOS==7))#((HPOS==429)&(VPOS==269))) then VSDUR := 0;
	else VSDUR := VSDUR.FB;
//trandition of EQ duration signal
	when(((HPOS==0)&(VPOS==1))#((HPOS==429)&(VPOS==263))) then EQDUR := 1;
	else when(((HPOS==0)&(VPOS==10))#((HPOS==429)&(VPOS==272))) then EQDUR := 0;
	else EQDUR := EQDUR.FB;
//condition of CSYNC down
	when(H20 # (EQDUR & H449)) then CSDOWN = 1;
	else CSDOWN = 0;
//condition of CSYNC up
	when(H385 # H814 # (!EQDUR & H84) # (EQDUR & !VSDUR & (H52 # H481))) then CSUP = 1;
	else CSUP = 0;
//CSYNC trandition
	when(CSUP) then CSYNC := 1;
	else when(CSDOWN) then CSYNC := 0;
	else CSYNC := CSYNC.FB;
}

END