MODULE dimmpc

LOGANA = 0;

CLK             pin;
STB             pin;
BUSY            pin istype 'pos,reg';
ACK             pin;
STBD            node istype 'pos,reg';
STBDD           node istype 'pos,reg';

HSYNC           node istype 'neg,com';
VSYNC           node istype 'neg,com';
CSYNC           node istype 'neg,com';
BLNK            node istype 'pos,com';
ENA             node istype 'pos,reg';
HSYNCD          node istype 'pos,reg';
VSYNCD          node istype 'pos,reg';
SYNCENA         node istype 'pos,com';
Q1..Q0          node istype 'pos,reg';

HREF            node istype 'pos,com';
GRID            node istype 'neg,com';
GRIDL           node istype 'neg,com';
ACTV            node istype 'pos,reg';
LOG7..LOG0      node istype 'pos,com';
LOGCKE          node istype 'pos,com';
HREFD           node istype 'pos,reg';
NEXTWRITE       node istype 'pos,reg';

RANDOM15..RANDOM0 node istype 'pos,reg';

MODE14          pin;
MODE13          pin;
MODE12          pin;
MODE11          pin istype 'pos,reg';
MODE10..MODE0   pin;

SDD15..SDD0     pin istype 'pos,com';
SDD47..SDD32    pin istype 'pos,com';

PD7..PD0        pin;
IOCLK           PIN istype 'pos,com';
IOD15..IOD0     PIN istype 'pos,reg';
XPOS9..XPOS0    node istype 'pos,reg';
YPOS7..YPOS0    node istype 'pos,reg';

PD = [PD7..PD0];
LOG = [LOG7..LOG0];
XPOS = [XPOS9..XPOS0];
YPOS = [YPOS7..YPOS0];
Q    = [Q1..Q0];

"------------------ for SDRAM DIMM -------------------

SDRAS           node istype 'pos,reg';
SDCAS           node istype 'pos,reg';
SDWE            node istype 'pos,reg';
SDBA1           node istype 'pos,reg';
SDBA0           node istype 'pos,reg';
SDA10           node istype 'pos,reg';
A10             node istype 'pos,com';
BA1             node istype 'pos,com';
BA0             node istype 'pos,com';
SDRES           node istype 'pos,com';
NEXT            node istype 'pos,reg';
DUMMY           node istype 'pos,com';

STSDC7..STSDC0  node istype 'reg';
ST_SDCON = [STSDC7..STSDC0];

SDCMD  =[SDRAS,SDCAS,SDWE,SDBA1,SDBA0,SDA10];
scNOP   = [1,  1,  1,.x.,.x.,.x.];
scBST   = [1,  1,  0,.x.,.x.,.x.];
scREAD  = [1,  0,  1,BA1,BA0,  0];
scREADA = [1,  0,  1,BA1,BA0,  1];
scWRIT  = [1,  0,  0,BA1,BA0,  0];
scWRITA = [1,  0,  0,BA1,BA0,  1];
scACT   = [0,  1,  1,BA1,BA0,A10];
scPRE   = [0,  1,  0,BA1,BA0,.x.];
scPALL  = [0,  1,  0,.x.,.x.,  1];
scREF   = [0,  0,  1,.x.,.x.,.x.];
scSELF  = [0,  0,  1,.x.,.x.,.x.];
scMRS   = [0,  0,  0,  0,  0,  0];

SDDPIN  = [0,SDD7.PIN,SDD6.PIN,SDD5.PIN,SDD4.PIN,SDD3.PIN,SDD2.PIN,SDD1.PIN];
SDDPINS = [0,       0,SDD7.PIN,SDD6.PIN,SDD5.PIN,SDD4.PIN,SDD3.PIN,SDD2.PIN];

EQUATIONS

[BLNK,LOGCKE,SYNCENA,GRIDL,GRID,HREF,CSYNC,HSYNC,VSYNC] = [MODE8..MODE0];

XPOS.CLK = CLK;
YPOS.CLK = CLK;
ENA.CLK = CLK;
ACTV.CLK = CLK;
HREFD.CLK = CLK;
HSYNCD.CLK = CLK;
VSYNCD.CLK = CLK;
[IOD15..IOD0].CLK = !CLK;
Q.CLK = CLK;
NEXTWRITE.CLK = CLK;
STBD.CLK = CLK;
STBDD.CLK = CLK;
[RANDOM15..RANDOM0].CLK = CLK;

NEXTWRITE := MODE9;

when(STBD & !STB) then{
	[RANDOM15..RANDOM8] := [RANDOM15..RANDOM8];
	[RANDOM7..RANDOM0] := PD.PIN;
}
else{
	[RANDOM15..RANDOM0] := [RANDOM15..RANDOM0].FB;
}

MODE11.CLK = CLK;

STBD  := STB;
STBDD := STBD;

when(!STBDD & STBD) then{
	MODE11 := 1;
}
else when(NEXTWRITE) then{
	MODE11 := 0;
}
else MODE11 := MODE11;

BUSY.CLK = CLK;
BUSY := MODE11;

when(NEXTWRITE) then{   // mode9 = NEXT IS WRITE
	SDD0.OE = 1;
	SDD1.OE = 1;
	SDD2.OE = 1;
	SDD3.OE = 1;
	SDD4.OE = 1;
	SDD5.OE = 1;
	SDD6.OE = 1;
	SDD7.OE = 1;
	SDD8.OE = 1;
	SDD9.OE = 1;
	SDD10.OE = 1;
	SDD11.OE = 1;
	SDD12.OE = 1;
	SDD13.OE = 1;
	SDD14.OE = 1;
	SDD15.OE = 1;
	[SDD15..SDD8] = 0;
	[SDD7..SDD0] = [RANDOM7..RANDOM0];
}
else{
	SDD0.OE = 0;
	SDD1.OE = 0;
	SDD2.OE = 0;
	SDD3.OE = 0;
	SDD4.OE = 0;
	SDD5.OE = 0;
	SDD6.OE = 0;
	SDD7.OE = 0;
	SDD8.OE = 0;
	SDD9.OE = 0;
	SDD10.OE = 0;
	SDD11.OE = 0;
	SDD12.OE = 0;
	SDD13.OE = 0;
	SDD14.OE = 0;
	SDD15.OE = 0;
}

when(HREF & !HREFD) then Q := 1;
else Q := Q.FB + 1;

ENA := SYNCENA;
HSYNCD := HSYNC;
VSYNCD := VSYNC;

when(!CSYNC) then{
    [IOD7..IOD0] := 0;
}
else{
    when(!HREF # BLNK) then{
        [IOD7..IOD0] := 64;
    }
    else{
        when(LOGANA) then {
            when(ACTV) then [IOD7..IOD0] := 192;
            else when(GRIDL) then [IOD7..IOD0] := 255;
            else when(GRID) then [IOD7..IOD0] := 128;
            else [IOD7..IOD0] := 64;
        }
        else{
			when([Q1..Q0] == 3) then [IOD7..IOD0] := SDDPIN + SDDPINS + 64;
			else [IOD7..IOD0] := [IOD7..IOD0];
		}
	}
}

DUMMY = MODE4 & MODE5;

[IOD15..IOD8]  := 0;
IOD8.OE = 0;
IOD9.OE = 0;
IOD10.OE = 0;
IOD11.OE = 0;

when(LOGCKE) then HREFD := HREF;
else HREFD := HREFD.FB;

when(!HSYNC) then XPOS := 0;
else when(LOGCKE & HREF) then XPOS := XPOS.FB + 1;
else XPOS := XPOS.FB;

when(!VSYNC) then YPOS := 0;
else{
    when(HSYNC & !HSYNCD) then YPOS := YPOS + 1; // +2
    else YPOS := YPOS.FB;
}

when(LOGANA) then {
    LOG0 = SDRAS;
    LOG1 = SDCAS;
    LOG2 = SDWE;
    LOG3 = SDBA1;
    "LOG4 = SDBA0;
    "LOG5 = SDA10;
    "LOG6 = LOGCKE & HREFD;
    "LOG7 = ([STSDC2..STSDC0] == 0);
    LOG4 = IOD8.PIN;
    LOG5 = IOD9.PIN;
    LOG6 = IOD10.PIN;
    LOG7 = IOD11.PIN;
}
else [LOG7..LOG0] = [SDD7..SDD0];

when([YPOS7..YPOS3] == 8) then{
    ACTV := LOG0;// +3
} 
else when([YPOS7..YPOS3] == 10) then{
    ACTV := LOG1;
} 
else when([YPOS7..YPOS3] == 12) then{
    ACTV := LOG2;
} 
else when([YPOS7..YPOS3] == 14) then{
    ACTV := LOG3;
} 
else when([YPOS7..YPOS3] == 16) then{
    ACTV := LOG4;
} 
else when([YPOS7..YPOS3] == 18) then{
    ACTV := LOG5;
} 
else when([YPOS7..YPOS3] == 20) then{
    ACTV := LOG6;
} 
else when([YPOS7..YPOS3] == 22) then{
    ACTV := LOG7;
} 
else ACTV := 0;

IOCLK = Q1;

"------------------ for SDRAM DIMM -------------------

ST_SDCON.CLK = CLK;
SDRAS.CLK = CLK;
SDCAS.CLK = CLK;
SDWE.CLK  = CLK;
SDBA1.CLK = CLK;
SDBA0.CLK = CLK;
SDA10.CLK = CLK;
SDRES = !HREF;
NEXT  := LOGCKE & HREFD;
NEXT.CLK = CLK;

State_diagram ST_SDCON;
state 0:
    SDCMD := scNOP;
    if(SDRES) then 0;
    else if(!NEXT) then 0;
    else 1;
state 1:
    SDCMD := scNOP;
    if(SDRES) then 0;
    else if(!NEXT) then 1;
    else 2;
state 2:
    SDCMD := scNOP;
    if(SDRES) then 0;
    else if(!NEXT) then 2;
    else 3;
state 3:
    SDCMD := scNOP;
    if(SDRES) then 0;
    else if(!NEXT) then 3;
    else 4;
state 4:
    BA1 = 0;
    BA0 = 0;
    A10 = 0;
    SDCMD := scACT;
    if(SDRES) then 0;
    else if(!NEXT) then 4;
    else 5;
state 5:
    BA1 = 0;
    BA0 = 0;
    SDCMD := scREADA;
    if(SDRES) then 0;
    else if(!NEXT) then 5;
    else 6;
state 6:
    SDCMD := scNOP;
    if(SDRES) then 0;
    else if(!NEXT) then 6;
    else 7;
state 7:
    SDCMD := scNOP;
    if(SDRES) then 0;
    else if(!NEXT) then 7;
    else 8;
state 8:
    BA1 = 0;
    BA0 = 1;
    A10 = 0;
    SDCMD := scACT;
    if(SDRES) then 0;
    else if(!NEXT) then 8;
    else 9;
state 9:
    BA1 = 0;
    BA0 = 1;
    SDCMD := scWRITA;
    if(SDRES) then 0;
    else if(!NEXT) then 9;
    else 10;
state 10:
    SDCMD := scNOP;
    if(SDRES) then 0;
    else if(!NEXT) then 10;
    else 11;
state 11:
    SDCMD := scNOP;
    if(SDRES) then 0;
    else if(!NEXT) then 11;
    else 12;
state 12:
    SDCMD := scSELF;
    if(SDRES) then 0;
    else if(!NEXT) then 12;
    else 13;
state 13:
    SDCMD := scNOP;
    if(SDRES) then 0;
    else if(!NEXT) then 13;
    else 14;
state 14:
    SDCMD := scNOP;
    if(SDRES) then 0;
    else if(!NEXT) then 14;
    else 15;
state 15:
    SDCMD := scNOP;
    if(SDRES) then 0;
    else if(!NEXT) then 15;
    else 4;

END