MODULE dimmpa
CLK PIN;
[Q1..Q0] node istype 'pos,reg';
[MODE14..MODE0]	pin;

Q = [Q1..Q0];

HREF  		node;
HREFD 		node istype 'pos,reg';
LOGCKE		node istype 'pos,com';
CSYNC		node istype 'pos,com';
VSYNC		node istype 'pos,com';
VSYNCD		node istype 'pos,reg';
VSYNCDD		node istype 'pos,reg';
HSYNC		node istype 'pos,com';

XSYNC		node istype 'pos,com';
TEST_OP0	pin istype 'pos,com';
TEST_OP1	pin istype 'pos,com';
TEST_OP2	pin istype 'pos,com';
TEST_OP3	pin istype 'pos,com';
TEST_OP4	pin istype 'pos,com';
TEST_OP5	pin istype 'pos,com';
TEST_OP6	pin istype 'pos,com';
TEST_OP7	pin istype 'pos,com';

"------------------ for SDRAM DIMM -------------------

SDRAS			pin istype 'pos,reg';
SDCAS			pin istype 'pos,reg';
SDWE			pin istype 'pos,reg';
SDBA1			pin istype 'pos,reg';
SDBA0			pin istype 'pos,reg';
BA1				node istype 'pos,com';
BA0				node istype 'pos,com';
SDRES			node istype 'pos,com';
NEXT 			node istype 'pos,reg';
SDCKE0			pin istype 'pos,com';
SDCK0			pin istype 'pos,com';
SDCK1			pin istype 'pos,com';
SDCK2			pin istype 'pos,com';
SDCK3			pin istype 'pos,com';
DQMBL			pin istype 'pos,com';
DQMBH			pin istype 'pos,com';
SDS01			pin istype 'pos,com';
SDS23			pin istype 'pos,com';
[RA23..RA0] 	node istype 'pos,reg';
[WA23..WA0] 	node istype 'pos,reg';

READ_RASADDR	node istype 'pos,reg';
READ_CASADDR	node istype 'pos,reg';
WRITE_RASADDR	node istype 'pos,reg';
WRITE_CASADDR	node istype 'pos,reg';
MRSADDR			node istype 'pos,reg';
READ_ADDRINC 	node istype 'pos,reg';
WRITE_ADDRINC 	node istype 'pos,reg';

RADDR = [RA23..RA0];
WADDR = [WA23..WA0];

[SDA11..SDA0] 	pin istype 'pos,reg';
[SDXA9..SDXA0] 	node istype 'pos,reg';
SDA = [SDA11..SDA0];
SDXA = [SDXA9..SDXA0];

STSDC7..STSDC0 	node istype 'reg';
ST_SDCON = [STSDC7..STSDC0];

SDCMD    = [SDRAS,SDCAS,SDWE,SDBA1,SDBA0];
scNOP    = [1,  1,  1,.x.,.x.];
scBST    = [1,  1,  0,.x.,.x.];
scREAD   = [1,  0,  1,BA1,BA0];
scREADA  = [1,  0,  1,BA1,BA0];
scWRITE  = [1,  0,  0,BA1,BA0];
scWRITEA = [1,  0,  0,BA1,BA0];
scACT    = [0,  1,  1,BA1,BA0];
scPRE    = [0,  1,  0,BA1,BA0];
scPALL   = [0,  1,  0,.x.,.x.];
scREF    = [0,  0,  1,.x.,.x.];
scSELF   = [0,  0,  1,.x.,.x.];
scMRS    = [0,  0,  0,BA1,BA0];

EQUATIONS

HREF  = MODE3;
CSYNC = MODE2;
HSYNC = MODE1;
VSYNC = MODE0;
LOGCKE = MODE7;
XSYNC = VSYNC & HSYNC & CSYNC & LOGCKE;

Q.CLK = CLK;
HREFD.CLK = CLK;
SDA.CLK = CLK;
SDXA.CLK = CLK;
SDRAS.CLK = CLK;
SDCAS.CLK = CLK;
SDWE.CLK = CLK;
SDBA1.CLK = CLK;
SDBA0.CLK = CLK;
NEXT.CLK = CLK;
RADDR.CLK = CLK;
WADDR.CLK = CLK;
VSYNCD := VSYNC;
VSYNCDD := VSYNCD;
VSYNCD.CLK = CLK;
VSYNCDD.CLK = CLK;

TEST_OP0 = STSDC0;
TEST_OP1 = STSDC1;
TEST_OP2 = STSDC2;
TEST_OP3 = STSDC3;
TEST_OP4 = STSDC4;
TEST_OP5 = STSDC5;
TEST_OP6 = STSDC6;
TEST_OP7 = STSDC7;

HREFD := HREF;
SDCK0 = !CLK;
SDCK1 = !CLK;
SDCK2 = !CLK;
SDCK3 = !CLK;
SDCKE0 = 1;
DQMBL = 0;
DQMBH = 1;
SDS01 = 0;
SDS23 = 1;

when(HREF & !HREFD) then Q := 1;
else Q := Q.FB + 1;

READ_RASADDR.CLK = CLK;
READ_CASADDR.CLK = CLK;
READ_ADDRINC.CLK = CLK;
WRITE_RASADDR.CLK = CLK;
WRITE_CASADDR.CLK = CLK;
WRITE_ADDRINC.CLK = CLK;
MRSADDR.CLK = CLK;

when(WRITE_ADDRINC) then{
	when([WA9..WA0] == 767) then{
		[WA9..WA0] := 0;
		when([WA19..WA10] == 524) then [WA19..WA10] := 0;
		else [WA19..WA10] := [WA19..WA10] + 1;
	}
	else{
		[WA9..WA0] := [WA9..WA0] + 1;
		[WA19..WA10] := [WA19..WA10];
	}
}
else{
	[WA19..WA0] := [WA19..WA0];
}

[WA23..WA20] := 0;

when(READ_RASADDR) then{
	BA1   = 0;
	BA0   = 0;
	SDA11 := 0;
	SDA10 := RA9;
"	[SDA9..SDA0] := [0,0,1,1,1,1,RA16..RA13];
"	[SDXA9..SDXA0] := [0,0,0,0,0,0,RA7..RA4];
	[SDA9..SDA0] := [RA19..RA10];
	[SDXA9..SDXA0] := [RA9..RA0];
}
else when(READ_CASADDR) then{
	BA1   = 0;
	BA0   = 0;
	SDA11 := 0;
	SDA10 := 1; // Auto precharge
	[SDA9..SDA0] := [SDXA9..SDXA0];
	[SDXA9..SDXA0] := [RA9..RA0];
}
else when(WRITE_RASADDR) then{
	BA1   = 0;
	BA0   = 0;
	SDA11 := 0;
	SDA10 := WA9;
	[SDA9..SDA0] := [WA19..WA10];
	[SDXA9..SDXA0] := [WA9..WA0];
}
else when(WRITE_CASADDR) then{
	BA1   = 0;
	BA0   = 0;
	SDA11 := 0;
	SDA10 := 1; // Auto precharge
	[SDA9..SDA0] := [SDXA9..SDXA0];
	[SDXA9..SDXA0] := [RA9..RA0];
}
else when(MRSADDR) then{
	BA1   = 0;
	BA0   = 0;
	SDA11 := 0;
	SDA10 := 0;
	SDA9  := 1;
	SDA8  := 0;
	SDA7  := 0;
	SDA6  := 0;
	SDA5  := 1;
	SDA4  := 0;
	SDA3  := 0;
	SDA2  := 0;
	SDA1  := 0;
	SDA0  := 0;
}

when(!HREFD) then [RA9..RA0] := 0;
else when(READ_ADDRINC) then{
	[RA9..RA0] := [RA9..RA0].FB + 1;
}
else [RA9..RA0] := [RA9..RA0].FB;

when(MODE10) then [RA19..RA10] := 0;
else when(!HREFD & HREF) then [RA19..RA10] := [RA19..RA10].FB + 1;
else [RA19..RA10] := [RA19..RA10].FB;

[RA23..RA20] := 0;

ST_SDCON.CLK = CLK;
SDRAS.CLK = CLK;
SDCAS.CLK = CLK;
SDWE.CLK  = CLK;
SDBA1.CLK = CLK;
SDBA0.CLK = CLK;
SDA10.CLK = CLK;
SDRES = !HREF;
NEXT  := 1 # (LOGCKE & HREFD);
NEXT.CLK = CLK;
MODE9 = WRITE_RASADDR;

"when(!VSYNCD & VSYNCDD) then WRITE_ADDRINC := 1;
"else WRITE_ADDRINC := 0;

State_diagram ST_SDCON;
state 0:
	SDCMD := scNOP;
	goto 1;
state 1:
	SDCMD := scNOP;
	if(!VSYNC) then 2;
	else 1;
state 2:
	SDCMD := scNOP;
	if(VSYNC) then 3;
	else 2;
state 3:
	SDCMD := scNOP;
	if(!VSYNC) then 4;
	else 3;
state 4:
	SDCMD := scPALL;
	goto 5;
state 5:
	SDCMD := scNOP;
	goto 6;
state 6:
	SDCMD := scNOP;
	goto 7;
state 7:
	SDCMD := scNOP;
	MRSADDR := 1;
	goto 8;
state 8:
	SDCMD := scMRS;
	goto 9;
state 9:
	SDCMD := scNOP;
	goto 10;
state 10:
	SDCMD := scNOP;
	goto 11;
state 11:
	SDCMD := scNOP;
	goto 12;
state 12:              " WRITE START
	SDCMD := scNOP;
	if(MODE11) then 13
	else 17
state 13:
	SDCMD := scNOP;
	WRITE_RASADDR := 1;
	goto 14;
state 14:
	SDCMD := scACT;
	WRITE_CASADDR := 1;
	goto 15;
state 15:
	SDCMD := scWRITEA;
	WRITE_ADDRINC := 1;
	goto 20;
state 16:
	SDCMD := scNOP;
	goto 17;
state 17:
	SDCMD := scNOP;
	goto 18;
state 18:
	SDCMD := scNOP;
	goto 19;
state 19:
	SDCMD := scNOP;
	goto 20;
state 20:
	SDCMD := scREF;
	goto 21;
state 21:
	SDCMD := scNOP;
	goto 22;
state 22:
	SDCMD := scNOP;
	goto 23;
state 23:
	SDCMD := scNOP;
	if (SDRES) then 20
	else 24
state 24:                    " READ START
	SDCMD := scNOP;
	READ_RASADDR := 1;
	goto 25;
state 25:
	SDCMD := scACT;
	READ_CASADDR := 1;
	goto 26;
state 26:
	SDCMD := scREAD;
	goto 27;
state 27:
	SDCMD := scNOP;
	READ_ADDRINC := 1;
	if(SDRES) then 12;
	else 24;
state 28:
	SDCMD := scNOP;
	goto 29;
state 29:
	SDCMD := scNOP;
	goto 30;
state 30:
	SDCMD := scNOP;
	goto 31;
state 31:
	SDCMD := scNOP;
	WRITE_ADDRINC := 1;
	goto 24;

END